1. Field of the Invention
The present invention relates to a semiconductor memory device and to a method for manufacturing same. More particularly, it relates to a semiconductor memory device having redundant cells, in which failed cells are repaired using row redundancy or column redundancy of the prior art, and further in which remaining failed cells not repairable using row redundancy or column redundancy are repaired by increasing the number of refreshes thereby repairing these cells and increasing manufacturing yield.
2. Related Art
FIG. 11 of the accompanying drawings is a conventional block diagram showing the configuration of a semiconductor memory device.
In FIG. 11, the reference numeral 1 denotes a memory array, 2 is a peripheral circuit, 3 is a switch, 4 is a row pre-decoder, 5 is a redundant X decoder, and 6 is a CBR counter, this semiconductor memory device in FIG. 11 is provided with a plurality of separated segments which serve as repair units (in the drawing, a row has 4 segments and a column has 2 segments).
A row address generated by the peripheral circuit 2 is input to a switch 3. The output of the switch 3 is input to the row pre-decoder 4 and the redundant X decoders 5. At the time of input of an active command for the purpose of writing into or reading from the memory cell 1, a row address output from the peripheral circuit 2 is input to the row pre-decoder 4 and the redundant X decoder 5 via the switch 3.
At the time of input of a refresh command for the purpose of performing a refresh operation, an internal address counted up within the CBR counter 6, based on a CBR signal generated in accordance with a refresh command, is input to the row pre-decoder 4 and the redundant X decoder 5 via the switch 3.
Each of the redundant X decoders 5 has X3 to X10 of the row addresses input to it, the logic of X11 and X12 of row pre-decoder outputs being input as enabling logic to the redundant X decoder 5.
The logic of the X3 to X12 outputs of the row pre-decoder 4 is input to the X decoders (XDEC) 7 and performs selection of the main word line, and the logic of X0 to X2 is input to the memory array 1, and used to select the sub-word lines, 8 lines of which are provided for each main word line.
The address incrementing within the CBR counter 6 is performed once for each input of a refresh command.
When the output signal (the internal row address) of the switch 3 that is input to the redundant X decoders 5 coincides with the row redundancy address programmed within the redundant X decoders 5, all of the main word lines decoded by the X decoders 7 (XDEC) are deselected, and in their place, the redundant main word lines decoded by the redundant X decoders 5 are selected.
In the same manner, when the column address input to the redundant Y decoders 8 coincides with a column redundancy address that is programmed within the redundant Y decoders 8 in the manufacturing process, all of the column selection lines decoded by the Y decoders (YDEC) 9 become deselected, and in their place the redundancy column selection lines output from the redundant Y decoders 8 are selected.
The reference numeral 10 denotes an input/output circuit for the purpose of reading out data from the memory array 1 or writing data to the memory array 1.
In the process of repairing failed cells in the conventional semiconductor memory device configured as noted above, there is the problem that in the case in which all the redundant circuits are quickly used up in one segment, even if there are remaining usable redundant circuits in other segments, because the above-noted segment has used up all its redundant circuits, it becomes impossible to repair this semiconductor memory device.
In a method of repairing such a semiconductor memory device, there is the additional problem of increased chip cost, caused by the need to provide a greater number of redundant cells.
The Japanese Unexamined Patent Publication (KOKAI) No. 4-10297 has been proposed to improve the above-described problems. This Patent Publication describes that it is possible to reduce the chip surface area and reduce the cost by performing refresh of a specific cell having poor refresh characteristics more frequently than other cells.
The inventor of the present invention, taking note of the causes of failed cells, and in particular poor refresh characteristics, realized that if it were possible to improve the refresh characteristics of a failed cell and perform a refresh at a period that was shorter than the refresh period of a usual cell, it would be possible to repair more failed cells, this concept leading to the invention of a novel method of repairing failed cells.
Given the above, it is an object of the present invention to provide a novel semiconductor memory device and method for manufacturing same, which improves manufacturing yield, and which provides a further improvement in stable operation over what is described in the above-noted Patent Publication.